The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2007
Filed:
Apr. 11, 2002
Dynamic determination of memory mapped input output range granularity for multi-node computer system
Prabhunandan B. Narasimhamurthy, San Jose, CA (US);
Yukio Nishimura, Ishikawa-ken, JP;
Sudheer Miryala, San Jose, CA (US);
Kazunori Masuyama, Kanagawa, JP;
Prabhunandan B. Narasimhamurthy, San Jose, CA (US);
Yukio Nishimura, Ishikawa-ken, JP;
Sudheer Miryala, San Jose, CA (US);
Kazunori Masuyama, Kanagawa, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A method and system enables dynamic support of memory mapping devices in a multi-node computer system. One of central process unit (CPU) nodes determines a total amount of MMIO address spaces that are needed for all MMIO devices and generates an optimized granularity to support the total amount of MMIO address spaces. Based on the granularity, a CPU node controller configures MMIO range registers of the interconnect and other MMIO registers in IO nodes and CPU node controllers to support dynamic changes of MMIO address space requirements of the system.