The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2007
Filed:
Jun. 20, 2005
Akira Kikutake, Kawasaki, JP;
Yasuhiro Onishi, Kawasaki, JP;
Kuninori Kawabata, Kawasaki, JP;
Junichi Sasaki, Kawasaki, JP;
Toshiya Miyo, Kawasaki, JP;
Akira Kikutake, Kawasaki, JP;
Yasuhiro Onishi, Kawasaki, JP;
Kuninori Kawabata, Kawasaki, JP;
Junichi Sasaki, Kawasaki, JP;
Toshiya Miyo, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
Regular data inputted/outputted to/from external terminals is read/written to/from a regular cell array, and parity data is read/written from/to a parity cell array. Since the parity data is generated by a parity generation circuit, it is difficult to write a desired pattern to the parity cell array. The regular data and the parity data are exchanged with each other by a switch circuit, so that the regular data can be written to the parity cell array and the parity data can be written to the regular cell array. This enables the write of desired data to the parity cell array. A test of the parity data can be easily conducted. In particular, a leakage test or the like between memory cells can be easily conducted.