The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 01, 2007
Filed:
Aug. 23, 2005
Shi-dong Zhou, Milpitas, CA (US);
Gubo Huang, Milpitas, CA (US);
Shi-dong Zhou, Milpitas, CA (US);
Gubo Huang, Milpitas, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A test-mode circuit allows the same pad of a semiconductor device to be used as a test pad during test operations and as an I/O pad during normal operations. The test-mode circuit is coupled between the pad and a reference signal (Vbg) of the device, and in response to a control signal (CTRL) either couples the pad and the reference signal (Vbg) together or isolates the pad and the reference signal (Vbg) from each other. The test-mode circuit includes at least one NMOS transistor (MN) and a PMOS transistor (MP) connected in series between the pad and the reference signal (Vbg). During normal operation, the NMOS transistor (MN) isolates the reference signal (Vbg) from the pad, and the PMOS transistor (MP) compensates for voltage undershoot conditions at the pad.