The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 01, 2007

Filed:

Apr. 22, 2005
Applicant:

Chien-sheng Yang, Taipei, TW;

Inventor:

Chien-Sheng Yang, Taipei, TW;

Assignee:

AU Optronics Corp., Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An ion sensitive field effect transistor (ISFET) and a fabrication method of the same are disclosed including a non-single-crystal silicon-base substrate, a polysilicon layer, a source, a drain, an insulating layer, a first electrode, a second electrode, a passivation layer, and an ion sensitive gate. The polysilicon layer is formed above the non-single-crystal silicon-base substrate, the source and the drain are formed in the polysilicon layer, and a predetermined channel region is formed in the polysilicon layer between the source and the drain. The insulating layer is formed above the polysilicon layer including a first contact hole and a second contact hole. The first electrode and the second electrode are electrically couple to the source and the drain by the first contact hole and the second contact hole, respectively. The passivation layer is formed above the insulating layer covering the first electrode and the second electrode, including an opening, which partially exposes the insulating layer above the predetermined channel region. The ion sensitive gate is formed in the opening above the insulating layer.


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