The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Dec. 02, 2003
Ciaran J. Brennan, Essex Junction, VT (US);
Steven M. Eustis, Essex Junction, VT (US);
Michael T. Fragano, Essex Junction, VT (US);
Michael R. Ouellette, Westford, VT (US);
Neelesh G. Pai, Williston, VT (US);
Jeremy P. Rowland, Essex Junction, VT (US);
Kevin M. Tompsett, Summit, NJ (US);
David J. Wager, South Burlington, VT (US);
Ciaran J. Brennan, Essex Junction, VT (US);
Steven M. Eustis, Essex Junction, VT (US);
Michael T. Fragano, Essex Junction, VT (US);
Michael R. Ouellette, Westford, VT (US);
Neelesh G. Pai, Williston, VT (US);
Jeremy P. Rowland, Essex Junction, VT (US);
Kevin M. Tompsett, Summit, NJ (US);
David J. Wager, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of manufacturing a device having embedded memory including a plurality of memory cells. During manufacturing test, a first test stress is applied to selected cells of the plurality of memory cells with a built-in self test. At least one weak memory cell is identified. The at least one weak memory cell is repaired. A second test stress is applied to the selected cells and the repaired cells with the built-in self test.