Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme

Abstract

Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than or smaller than a voltage VCCA/2 using an auxiliary circuit is used to increase a gate-source voltage of transistors included in each sense amplification circuit. Also, when cell data is 1 and 0, a dummy cell can maintain a voltage difference between the bitlines BL and BLB generated after charge sharing. Furthermore, a sense amplification circuit, which is controlled by an offset control circuit, can remove a threshold voltage offset between the transistors included in each sense amplification circuit. At this time, an auxiliary circuit is used to stabilize the voltage difference.