The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Feb. 10, 2003
Henning Hauenstein, El Segundo, CA (US);
Rainer Topp, Reutlingen, DE;
Jochen Seibold, Tuebingen, DE;
Dirk Balszunat, Tuebingen, DE;
Stefan Ernst, Ostfildern, DE;
Wolfgang Feiler, Reutlingen, DE;
Thomas Koester, Reutlingen, DE;
Stefan Hornung, Leinfelden-Echterdingen, DE;
Dieter Streb, Reutlingen, DE;
Henning Hauenstein, El Segundo, CA (US);
Rainer Topp, Reutlingen, DE;
Jochen Seibold, Tuebingen, DE;
Dirk Balszunat, Tuebingen, DE;
Stefan Ernst, Ostfildern, DE;
Wolfgang Feiler, Reutlingen, DE;
Thomas Koester, Reutlingen, DE;
Stefan Hornung, Leinfelden-Echterdingen, DE;
Dieter Streb, Reutlingen, DE;
Robert Bosch GmbH, Stuttgart, DE;
Abstract
A semiconductor component that is able to be produced simply, quickly, and yet reliably and that usable for power applications, and including a semiconductor chip, a lower, first main electrode layer formed on a first side of the semiconductor chip, a lower control electrode layer formed on the first side, an insulation layer formed on the first side between the lower first main electrode layer and the lower control electrode layer and which partly covers the lower first main electrode layer, an upper first main electrode layer which is formed on the lower first main electrode layer, an upper control electrode layer which is formed on the lower control electrode layer and the insulation layer and extends on the insulation layer partially above the lower first main electrode layer, and a second main electrode layer formed on a second side of the semiconductor chip.