The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Apr. 30, 2004
Yoshi Ono, Camas, WA (US);
Wei Gao, Vancouver, WA (US);
John F. Conley, Jr., Camas, WA (US);
Osamu Nishio, Nara, JP;
Keizo Sakiyama, Nara Pref., JP;
Yoshi Ono, Camas, WA (US);
Wei Gao, Vancouver, WA (US);
John F. Conley, Jr., Camas, WA (US);
Osamu Nishio, Nara, JP;
Keizo Sakiyama, Nara Pref., JP;
Sharp Laboratories of America, Inc., Camas, WA (US);
Abstract
A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II–VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.