The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Apr. 08, 2005
Eric W. Beach, Tucson, AZ (US);
Philipp Steinmann, Unterschleissheim, DE;
Eric W. Beach, Tucson, AZ (US);
Philipp Steinmann, Unterschleissheim, DE;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A method of making integrated circuit thin film resistor includes forming a first dielectric layer (B) over a substrate and providing a structure to reduce variation of head resistivity thereof by forming a dummy fill layer (A) on the first dielectric layer, and forming a second dielectric layer (D) over the first dummy fill layer. A thin film resistor () is formed on the second dielectric layer (D). A first inter-level dielectric layer (A) is formed on the thin film resistor and the second dielectric layer. A first metal layer (A) is formed on the first inter-level dielectric layer and electrically contacts a portion of the thin film resistor. Preferably, the first dummy fill layer is formed as a repetitive pattern of sections such that the repetitive pattern is symmetrically aligned with respect to multiple edges of the thin-film resistor (). Preferably, the first dummy fill layer is formed so as to extend sufficiently far beyond ends of the thin-film resistor to ensure only a negligible amount of systematic resistance error due to misalignment.