The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Oct. 30, 2002
Chad Weintraub, Dresden, DE;
James F. Buller, Austin, TX (US);
Derick Wristers, Bee Cave, TX (US);
Jon Cheek, Austin, TX (US);
Chad Weintraub, Dresden, DE;
James F. Buller, Austin, TX (US);
Derick Wristers, Bee Cave, TX (US);
Jon Cheek, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
An insulated gate field effect transistor having reduced gate-drain overlap and a method for manufacturing the insulated gate field effect transistor. A gate structure is formed on a major surface of a semiconductor substrate. A source extension region and a drain extension region are formed in a semiconductor material using an angled implant. The source extension region extends under the gate structure, whereas the drain extension region is laterally spaced apart from the gate structure. A source region is formed in the semiconductor substrate and a drain region is formed in the semiconductor substrate, where the source and drain regions are laterally spaced apart from the gate structure. A source-side halo region is formed in the semiconductor substrate adjacent the source extension region.