The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 24, 2007
Filed:
Jun. 16, 2005
Shanjen Pan, Plano, TX (US);
Sameer Pendharkar, Allen, TX (US);
Pinghai Hao, Plano, TX (US);
James R. Todd, Plano, TX (US);
Shanjen Pan, Plano, TX (US);
Sameer Pendharkar, Allen, TX (US);
Pinghai Hao, Plano, TX (US);
James R. Todd, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Methods of fabrication and devices include field plates formed during capacitor formation. Isolation structures are formed in a semiconductor substrate. Well regions are formed in the semiconductor substrate. Drain extension regions are formed in the well regions. A gate dielectric layer is formed over the device. A gate electrode layer is formed that serves as the gate electrode and a bottom capacitor plate. The gate electrode and the gate dielectric layer are patterned to form gate structures. Source and drain regions are formed within the well regions and the drain extension regions. A silicide blocking layer is formed that also serves as a capacitor dielectric. Field plates and a top capacitor plate are formed on the blocking layer.