The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Aug. 04, 2004
Vyacheslav L. Zavadsky, Ottawa, CA;
Elmehdi Aitnouri, Nepean, CA;
Edward Keyes, Ottawa, CA;
Jason Abt, Kanata, CA;
Val Gont, Kanata, CA;
Stephen Begg, Ottawa, CA;
Vyacheslav L. Zavadsky, Ottawa, CA;
Elmehdi Aitnouri, Nepean, CA;
Edward Keyes, Ottawa, CA;
Jason Abt, Kanata, CA;
Val Gont, Kanata, CA;
Stephen Begg, Ottawa, CA;
Semiconductor Insights Inc., Ontario, CA;
Abstract
The method and apparatus in accordance with the present invention determines the locations of incorrectly connected polygons in a polygon representation of an integrated circuit layout. These incorrectly connected polygons result in short circuits, which often occur for major signal busses such as power and ground. It can be time-consuming to determine the exact location of the short. The invention includes the step of tessellating the polygon representation, including each conductive layer, into predetermined shapes such as triangles or trapezoids. Each of the triangles or trapezoids is then translated into a node for the development of a nodal network where nodes are connected directly to one another to represent shapes having edges adjacent to other shape edges. The current capacity of each connection between adjacent nodes is then specified. Two nodes that are electrically connected to the incorrectly connected polygons are selected and used as parameters for a network flow analysis algorithm. This algorithm determines the areas of high density where high flow is dictated by the triangle or trapezoid having the lowest current capacity. The areas of high density are flagged as points where short circuits may exist. These flagged points may then be investigated to confirm whether they are short circuits.