Hybrid carry look ahead/carry select adder including carry logic generating complementary hot carry signals, and method for producing the carry logic

Abstract

A binary adder circuit including a carry logic circuit and selection logic. The carry logic circuit uses group generate and propagate signals to produce complementary carry signals. The selection logic produces one of two presums dependent on the complementary carry signals. In a method for producing a carry logic circuit, a group generate logic function G=GOR GAND Pis to be performed. When G=C, G=C, arrival times of generate signals Gand G, are investigated. If Garrives before G, a complex AND-OR-INVERT gate is used, otherwise a cascaded pair of NAND gates is selected. To produce a complementary carry signal, a logic function G'=G′ AND G′ OR P′ is to be performed. If the generate signal G′ arrives before G′, a complex OR-AND-INVERT gate is used, otherwise a cascaded pair of NOR gates is selected.