The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
May. 14, 2003
Joseph Sylvester Chang, Singapore, SG;
Bah Hwee Gwee, Singapore, SG;
Kwen Siong Chong, Singapore, SG;
Joseph Sylvester Chang, Singapore, SG;
Bah Hwee Gwee, Singapore, SG;
Kwen Siong Chong, Singapore, SG;
Chang, Joseph Sylvester, Singapore, SG;
Gwee, Bah Hwee, Singapore, SG;
Abstract
A digital Parallel Multiplier has a Partial Product Generator, a First Stage Adder Circuit and a Final Stage Adder Circuit. The spurious switching in the First Stage Adder Circuit may be substantially reduced by synchronizing the input signals to the Adders in First Stage Adder Circuit. The reduced spurious switching reduces the power dissipation of the Multiplier. The timing of the input signals is synchronized by means of the Latch Adders having a Latch that is an integral part of an Adder. Consequently, the power dissipation and hardware overheads of the Latch Adders are low. The Latch Adders may be controlled by Control Signals, which may be generated by Control Circuits. The application of the Latch Adders may be applied to the Final Stage Adder Circuit to further reduce spurious switching and thereby further reduce the power dissipation.