The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 17, 2007

Filed:

Jun. 29, 2005
Applicants:

James B. Y. Tsui, Dayton, OH (US);

Stuart Mitchell Lopata, Pallsades Park, NJ (US);

Charles Richard Ward, Wellsboro, PA (US);

Inventors:

James B. Y. Tsui, Dayton, OH (US);

Stuart Mitchell Lopata, Pallsades Park, NJ (US);

Charles Richard Ward, Wellsboro, PA (US);

Assignee:

ITT Manufacturing Enterprises Inc., Wilmington, DE (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 23/00 (2006.01); G06F 19/00 (2006.01); G01S 13/00 (2006.01); G01S 7/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

An IFM receiver includes a hybrid for outputting I and Q signals from a received input signal; a first ADC for digitizing the I signal to produce a first digital signal at a sampling rate of 1/τ, and a second ADC for digitizing the Q signal to produce a second digital signal at the same sampling rate. A processor is configured to (a) delay the first and second digital signals by at least one sample time of τ, (b) count the number of samples produced having predetermined phase shifts, and (c) determine the frequency of the received input signal, based on the number of samples having the predetermined phase shifts. The first and second ADCs are each 1-bit analog-to-digital converters. The predetermined phase shifts of 0°, 90°, −90° and 180° are counted by the processor over a predetermined time interval.


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