The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Oct. 12, 2001
Applicants:
Randall L. Findley, Austin, TX (US);
Sajol C. Ghoshal, Austin, TX (US);
Gregory E. Beers, Austin, TX (US);
Inventors:
Randall L. Findley, Austin, TX (US);
Sajol C. Ghoshal, Austin, TX (US);
Gregory E. Beers, Austin, TX (US);
Assignee:
Agere Systems Inc., Allentown, PA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract
A phase-locked loop (PLL), a method of programmably adjusting a phase of a reference clock signal and a synchronous sequential logic circuit incorporating the PLL or the method. In one embodiment, the PLL includes: (1) a digital feedback delay line having a plurality of taps and (2) tap selection logic, coupled to the digital feedback delay line, for activating one of the plurality of taps and thereby insert a corresponding delay into the PLL.