The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Dec. 14, 2005
Chiharu Koshio, Yamanashi-ken, JP;
Kimio Amemiya, Yamanashi-ken, JP;
Toshihiro Komaki, Yamanashi-ken, JP;
Hitoshi Taniguchi, Yamanashi-ken, JP;
Tatsuro Sakai, Yamanashi-ken, JP;
Kosuke Masuda, Yamanashi-ken, JP;
Chiharu Koshio, Yamanashi-ken, JP;
Kimio Amemiya, Yamanashi-ken, JP;
Toshihiro Komaki, Yamanashi-ken, JP;
Hitoshi Taniguchi, Yamanashi-ken, JP;
Tatsuro Sakai, Yamanashi-ken, JP;
Kosuke Masuda, Yamanashi-ken, JP;
Pioneer Corporation, Tokyo, JP;
Abstract
A plasma display panel comprises a front substrate and a rear substrate, a plurality of row electrode pairs provided on the inner surface of the front substrate, a dielectric layer provided on the inner surface of the front substrate for coverring the row electrode pairs, a plurality of column electrodes provided on the inner surface of the rear substrate, a partition wall assembly provided between the front substrate and the rear substrate, said partition wall assembly including a plurality of longitudinal partition walls and a plurality of lateral partition walls, forming a plurality of discharge cells. In particular, the dielectric layer has a plurality of projection portions located corresponding to and protruding toward the lateral partition walls of the partition wall assembly, in a manner such that there would be no slots formed between the dielectric layer and the lateral partition walls.