The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 17, 2007
Filed:
Jan. 15, 2004
Yukiko Furukawa, Leuven, BE;
Yukiko Furukawa, Leuven, BE;
NXP, B.V., Eindhoven, NL;
Abstract
The invention relates to a method of manufacturing a semiconductor device () with a semiconductor body () and a substrate () comprising at least one semiconductor element () and provided with at least one connection region () and an overlying stripe-shaped connection conductor () which is connected to the connection region (), which connection conductor and connection region are both recessed in a dielectric material, where subsequently a first dielectric layer (), a hard mask layer (), and a second dielectric layer () are deposited on the semiconductor body (), where at the location of the connection region () to be formed, a via () is formed in the first dielectric layer () by means of plasma etching using a plasma containing a compound of carbon and fluor, and in the presence of a patterned photoresist layer deposited on top of the structure and at the location of the connection conductor () to be formed, a trench () is formed in the second dielectric layer () by means of plasma etching, which via () and trench () are filled with an electrically conducting material in order to form, respectively, the connection region () and the connection conductor (), and where before the trench () is formed, the already formed via () is filled with an organic material (). According to the invention, the material of the first dielectric layer () and the etch conditions during formation of the via () in the first dielectric layer () by plasma etching are chosen such that during etching the via (), said via (),said via () is at the same time substantially completely filled with the organic material (), which organic material () is formed from organic material already present within the structure and within the plasma. Relevant conditions—apart from the presence of the resist layer during etching and the use therein of a compound of carbon and fluor—relate to the choice of the material of the first (and second) dielectric layer(s)and the power during etching of these layers ().