The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2007

Filed:

Jun. 01, 2004
Applicants:

Robert Anson Hamilton, Mountain View, CA (US);

Stanley Ted Jefferson, Palo Alto, CA (US);

Randy Allen Coverstone, Newark, CA (US);

Inventors:

Robert Anson Hamilton, Mountain View, CA (US);

Stanley Ted Jefferson, Palo Alto, CA (US);

Randy Allen Coverstone, Newark, CA (US);

Assignee:

Agilent Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/455 (2006.01);
U.S. Cl.
CPC ...
Abstract

A development environment includes a graphical design tool and a build agent. The graphical design tool allows a designer to design a primary logic component of a circuit. The graphical design tool generates modules using a hardware description language to represent the primary logic component of the circuit. The modules include abstract references to infrastructure for the circuit. The build agent synthesizes the modules into netlists and merges the netlists with a description of the infrastructure for the circuit. The infrastructure is generated in a development environment separate from the graphical design tool. The build agent includes an adjuster that adjusts the modules. The adjustment to the modules includes replacing the abstract references to the infrastructure with actual references utilized within the infrastructure.


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