The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Mar. 14, 2003
Roger B. Milne, Boulder, CO (US);
L. James Hwang, Menlo Park, CA (US);
Jeffrey D. Stroomer, Lafayette, CO (US);
Nabeel Shirazi, San Jose, CA (US);
Haibing MA, Superior, CO (US);
Jonathan B. Ballagh, Longmont, CO (US);
Roger B. Milne, Boulder, CO (US);
L. James Hwang, Menlo Park, CA (US);
Jeffrey D. Stroomer, Lafayette, CO (US);
Nabeel Shirazi, San Jose, CA (US);
Haibing Ma, Superior, CO (US);
Jonathan B. Ballagh, Longmont, CO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for simulating operations of a circuit design that includes high-level components and HDL components. The high-level components of the design are simulated in a high-level modeling system (HLMS), and the HDL components of the design are simulated with an HDL simulator. Data values are converted from a data type of the HLMS to a logic vector compatible with the HDL simulator for each data value to be input to the HDL simulator, and a logic vector is converted from the HDL simulator to a data value of a data type compatible with the HLMS for each logic vector output from the HDL simulator. Events are scheduled for input to the HDL simulator as a function of the time of HLMS events and a maximum response time of the HDL components.