The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Oct. 10, 2003
William Clay Boose, Howe, TX (US);
Vernon D. Davis, Mesquite, TX (US);
Peter D. Hanish, Richardson, TX (US);
William Clay Boose, Howe, TX (US);
Vernon D. Davis, Mesquite, TX (US);
Peter D. Hanish, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An automated test system () for testing a high-speed communications integrated circuit (), such as a serializer/deserializer, is disclosed. The system () is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit () are connected to serial input terminals (SERRX) of the integrated circuit (). An attenuator (), which in the disclosed embodiment includes programmable attenuators (P,N) and a fixed attenuator (), one of which is selected, is disposed in the loopback path. A deterministic jitter injector () is also in the loopback path, and may be implemented by way of variable length trace blocks (P,N) on the test board (). In this way, the serial output signals generated by the integrated circuit () are modified by the attenuator () and deterministic jitter injector () so that the signal as received at the serial input terminals (SERRX) can be at the specification limits of the circuit ().