The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2007

Filed:

May. 13, 2003
Applicants:

Carol Moy, Morristown, NJ (US);

Christine Divincenzo, Califon, NJ (US);

Eoin Carey, Cork, IE;

Herbert Jaeger, Cork, IE;

Robert Servilio, Washington, NJ (US);

Inventors:

Carol Moy, Morristown, NJ (US);

Christine DiVincenzo, Califon, NJ (US);

Eoin Carey, Cork, IE;

Herbert Jaeger, Cork, IE;

Robert Servilio, Washington, NJ (US);

Assignees:

M/A-Com, Inc., Lowell, MA (US);

M/A-Com, Eurotec, B.V., Amsterdam, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

A phase locked loop includes a buffer that synchronizes the transmission of the new count value to the completion of the previous count to avoid errors caused by dithering. The buffer is connected to a count input of the counter and transmits the new count upon receipt of the carryout signal from the counter. Alternatively, the transmission of the new value of N from the buffer is delayed after receipt by the buffer of a carryout signal from the counter. In another embodiment, a delayed version of the carryout signal is used to trigger the buffer to transmit the new count value to the counter. In another feature, a buffer synchronizes phase data to a reference signal before inputting it to a digital modulator of the phase locked loop.


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