The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Nov. 14, 2002
Bruce J. Currivan, Irvine, CA (US);
Ravi Bhaskaran, Irvine, CA (US);
Thomas J. Kolze, Phoenix, AZ (US);
Kevin Lee Miller, Lawrenceville, GA (US);
Jeffrey S. Putnam, Irvine, CA (US);
Fang LU, Rowland Heights, CA (US);
Tak K. Lee, Irvine, CA (US);
Thuji S. Lin, Irvine, CA (US);
Loke Kun Tan, Irvine, CA (US);
Gopal Triplicane Venkatesan, Aliso Viejo, CA (US);
Hsin-an Liu, Irvine, CA (US);
Jonathan S. Min, Buena Park, CA (US);
James P. Cavallo, Laguna Niguel, CA (US);
Bruce J. Currivan, Irvine, CA (US);
Ravi Bhaskaran, Irvine, CA (US);
Thomas J. Kolze, Phoenix, AZ (US);
Kevin Lee Miller, Lawrenceville, GA (US);
Jeffrey S. Putnam, Irvine, CA (US);
Fang Lu, Rowland Heights, CA (US);
Tak K. Lee, Irvine, CA (US);
Thuji S. Lin, Irvine, CA (US);
Loke Kun Tan, Irvine, CA (US);
Gopal Triplicane Venkatesan, Aliso Viejo, CA (US);
Hsin-An Liu, Irvine, CA (US);
Jonathan S. Min, Buena Park, CA (US);
James P. Cavallo, Laguna Niguel, CA (US);
Broadcom Corporation, Irvine, CA (US);
Abstract
All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.