Pll circuit and data read-out circuit

Abstract

Disclosed is a PLL circuit having a voltage-controlled oscillator, to which a difference voltage across non-inverting and inverting input terminals is input as a control voltage, for oscillating at a frequency in accordance with the control voltage; a phase comparator for comparing the phase of an output signal obtained by frequency-dividing the output of the voltage-controlled oscillator by a frequency-divider, with the phase of an input signal and outputting the result of this phase comparison; first and second loop filters connected at output terminals thereof to the non-inverting and inverting input terminals, respectively, of the voltage-controlled oscillator; and a charge pump, which is responsive to receipt of an UP signal supplied from the phase comparator, for supplying a first charging current from a PMOS transistor to a capacitor of the first loop filter and supplying a first discharge current from an NMOS transistor to a capacitor of the second loop filter, and which is responsive to receipt of a DOWN signal supplied from the phase comparator, for supplying a second charging current from a PMOS transistor to a capacitor of the second loop filter and supplying a second discharge current from an NMOS transistor to a capacitor of the first loop filter.