The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 10, 2007

Filed:

Sep. 30, 2004
Applicants:

Manuel P. Gabato, Jr., Elmhurst, IL (US);

Joseph A. Charaska, Melrose Park, IL (US);

Paul H. Gailus, Prospect Heights, IL (US);

Inventors:

Manuel P. Gabato, Jr., Elmhurst, IL (US);

Joseph A. Charaska, Melrose Park, IL (US);

Paul H. Gailus, Prospect Heights, IL (US);

Assignee:

Motorola, Inc., Schaumburg, IL (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A DPC () that includes: a frequency source (); a delay-locked loop () for receiving a clock signal and generating a plurality of phase-shifted clock signals; a control device () having a DPS () and a DAC () for receiving an input signal identifying a desired frequency for a synthesized signal; a selection circuit () for receiving the plurality of phase-shifted clock signals, selecting a sequence of the phase-shifted clock signals and outputting a coarse synthesized signal; a variable delay cell () having a first input coupled to the selection circuit to receive the coarse synthesized signal and a second input coupled to the control device for receiving a fine tune adjustment signal to modify the coarse synthesized signal to generate the synthesized signal () having substantially the desired frequency. The DPC further includes training apparatus for calibrating the DPC.


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