The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Nov. 18, 2004
Hung Cai Ngo, Austin, TX (US);
Jente Benedict Kuang, Austin, TX (US);
Harmander Singh Deogun, Lincoln, NE (US);
Aj Kleinosowski, Austin, TX (US);
Hung Cai Ngo, Austin, TX (US);
Jente Benedict Kuang, Austin, TX (US);
Harmander Singh Deogun, Lincoln, NE (US);
AJ Kleinosowski, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.