The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 10, 2007
Filed:
Mar. 24, 2004
Ramanath Ganapathiraman, Clifton Park, NY (US);
Ahila Krishnamoorthy, Virugambakkam, IN;
Kaushik Chanda, Poughkeepsie, NY (US);
Shyam P. Murarka, Clifton Park, NY (US);
Ramanath Ganapathiraman, Clifton Park, NY (US);
Ahila Krishnamoorthy, Virugambakkam, IN;
Kaushik Chanda, Poughkeepsie, NY (US);
Shyam P. Murarka, Clifton Park, NY (US);
Rensselaer Polytechnic Institute, Troy, NY (US);
Abstract
The present invention provides a method for forming a diffusion barrier layer, a diffusion barrier in an integrated circuit and an integrated circuit. The method for forming a diffusion barrier involves the following steps: 1) preparing a silicon substrate; 2) contacting the silicon substrate with a composition comprising self-assembled monolayer subunits and a solvent; and, 3) removing the solvent. The diffusion barrier layer includes a self-assembled monolayer. The integrated circuit includes a silicon substrate, a diffusion barrier layer and a metal deposited on the diffusion barrier layer. The diffusion barrier layer in the integrated circuit is covalently attached to the silicon substrate and includes a self-assembled monolayer.