Ferroelectric memory reference generator systems using staging capacitors

Abstract

Reference generator systems () and methods () are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (). The reference generator system () comprises a primary capacitance (), a precharge system () that charges the primary capacitance, and a reference system () with a plurality of local reference circuits () associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S) coupled between the staging capacitance and the primary capacitance (), and a second switching device (S, S) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S) couples the staging capacitance (Cs) to the precharged primary capacitance () and then isolates the precharged staging capacitance (Cs) from the primary capacitance (), and the second switching device (S, S) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.