The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Aug. 04, 2005
Tetsuya Tokunaga, Gunma-ken, JP;
Hiroyuki Arai, Gunma-ken, JP;
Takeshi Kimura, Tochigi-ken, JP;
Ryouichi Ando, Saitama-ken, JP;
Mamoru Yamaguchi, Gunma-ken, JP;
Tetsuya Tokunaga, Gunma-ken, JP;
Hiroyuki Arai, Gunma-ken, JP;
Takeshi Kimura, Tochigi-ken, JP;
Ryouichi Ando, Saitama-ken, JP;
Mamoru Yamaguchi, Gunma-ken, JP;
Sanyo Electric Co., Ltd., Osaka, JP;
Abstract
A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZPand ZPgenerated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.