The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 03, 2007

Filed:

Sep. 22, 2003
Applicants:

Guillaume DE Cremoux, Nijmegen, NL;

Insun Van Loo, Nijmegen, NL;

Jan Dikken, Nijmegen, NL;

Ferry Nieuwhoff, Nijmegen, NL;

Yovgos Christoforou, Nijmegen, NL;

Aykut Kenc, Nijmegen, NL;

Wilhelmus Johannes Remigius Willemsen, Nijmegen, NL;

Inventors:

Guillaume De Cremoux, Nijmegen, NL;

Insun Van Loo, Nijmegen, NL;

Jan Dikken, Nijmegen, NL;

Ferry Nieuwhoff, Nijmegen, NL;

Yovgos Christoforou, Nijmegen, NL;

Aykut Kenc, Nijmegen, NL;

Wilhelmus Johannes Remigius Willemsen, Nijmegen, NL;

Assignee:

DXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor switch comprises two NMOS transistors coupled in an anti-series arrangement, and a gate control circuit coupled to both gates of the NMOS transistors. Both drains of the NMOS transistors are interconnected, and the gate control circuit is coupled to the drains interconnection. The required chip area is halved compared to prior art switches. Pumping the gates to higher voltages may cause a further reduction of the sizes of the NMOS transistors. In addition, advantageously, a large range of input and output voltages can be allowed between the sources of the NMOS transistors, whereby the sources act as input and output respectively of the switch, thus allowing application of the switch in a broad technical field.


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