The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Jun. 20, 2003
Leon Maria Albertus Van DE Logt, Eindhoven, NL;
Franciscus Gerardus Maria DE Jong, Eindhoven, NL;
Leon Maria Albertus Van De Logt, Eindhoven, NL;
Franciscus Gerardus Maria De Jong, Eindhoven, NL;
NXP B.V., Eindhoven, NL;
Abstract
A test arrangement for testing the interconnections of an electronic circuit () and a further electronic circuit is provided. A first selection of I/O nodes (), which are arranged to receive input data in a functional mode of the electronic circuit (), and which are coupled to a test unit in a test mode of the electronic circuit (). The test unit has a combinatorial circuit () for implementing a multiple-input XOR or XNOR gate. The test unit also provides interconnections between the first selection of I/O nodes () and a second selection of I/O nodes () via logic gates (). These interconnections increase the interconnect test coverage of the electronic device (), because the interconnects with the further electronic circuits that are associated with I/O nodes () become testable as well.