The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 03, 2007
Filed:
Jan. 13, 2004
Nobuaki Takahashi, Kanagawa, JP;
Yuji Akimoto, Tokyo, JP;
Mikio Oda, Tokyo, JP;
Hikaru Kouta, Tokyo, JP;
Nobuaki Takahashi, Kanagawa, JP;
Yuji Akimoto, Tokyo, JP;
Mikio Oda, Tokyo, JP;
Hikaru Kouta, Tokyo, JP;
NEC Electronics Corporation, , JP;
NEC Corporation, , JP;
Abstract
Disclosed is a method of forming bump electrodes on wired circuit boards. A high-concentration impurity Si template doped with boron and having a pit formed therein is prepared. A plated resist is formed on the high-concentration impurity Si template and an opening is formed at the position of the pit. Then, an electric field is applied to the high-concentration impurity Si template and Au is buried in the opening in the plated resist to form a Au-plated buried layer. An electrode pad is formed on a semiconductor chip. With the plated resist separated from the high-concentration impurity Si template, the electrode pad of the semiconductor chip is aligned with the Au-plated buried layer and is bonded by thermo-compression bonding. The Au-plated buried layer is transferred to the electrode pad to form an Au bump on the semiconductor chip.