The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2007
Filed:
Oct. 05, 2005
Ananth Somayaji Goda, Bangalore, IN;
Kalpesh Amrutlal Shah, Bangalore, IN;
Prapanna Tiwari, Bangalore, IN;
Sugandhini Karunanidhi, Bangalore, IN;
Venugopal Puvvada, Bangalore, IN;
Ananth Somayaji Goda, Bangalore, IN;
Kalpesh Amrutlal Shah, Bangalore, IN;
Prapanna Tiwari, Bangalore, IN;
Sugandhini Karunanidhi, Bangalore, IN;
Venugopal Puvvada, Bangalore, IN;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.