The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2007

Filed:

Oct. 18, 2001
Applicants:

Deepak Mehta, Raritan, NJ (US);

Andrew Knight, Piscataway, NJ (US);

Deepak Sabharwal, Fremont, CA (US);

Raymond Tak-hoi, Palo Alto, CA (US);

Inventors:

Deepak Mehta, Raritan, NJ (US);

Andrew Knight, Piscataway, NJ (US);

Deepak Sabharwal, Fremont, CA (US);

Raymond Tak-Hoi, Palo Alto, CA (US);

Assignee:

Virage Logic Corp., Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A memory compiler characterization system and method for determining parametric data, wherein memory compilers of a first type are rigorously characterized and memory compilers of a second type are sparsely characterized with respect to a particular parameter. Absolute scale factors are determined based on the ratio of the parametric data points of two congruent memory compilers, one from each type. Interpolated scale factors are obtained based on the absolute scale factors. Parametric data for the remaining compilers of the sparsely characterized compiler set is filled out by applying the interpolated scale factors in conjunction with the data of the congruent memory compilers of the first type.


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