Serializer with programmable delay elements

Abstract

A two-bit serializer circuit as described herein includes programmable delay elements having adjustable phase delay that allows for phase tuning of two parallel input signals relative to an output multiplexer select signal. The two parallel input signals are retimed relative to a reference clock signal, and one of the retimed signals is processed by a fixed delay element. This delayed intermediate signal is further delayed using one programmable delay element; the other retimed signal is delayed using another programmable delay element. The delayed output signals generated by the programmable delay elements are utilized as input signals to a high speed output multiplexer. The multiplexer output select signal represents a buffered version of the reference clock signal. The programmable nature of the serializer circuit facilitates tuning to reduce jitter in the serialized output signal.