Memory array with current limiting device for preventing particle induced latch-up

Abstract

A memory device can include a group of memory cells, which can be arranged in a column () that receives power by way of a first cell supply nodes (-to-). A current limiter () can be situated between first cell supply nodes (-to-) and a power supply (VH), and limit a current (llimit) to less than a latch-up holding current (lhold_lu) for the group of memory cells (). In a particle event, such as an α-particle strike, a current limiter () can prevent a latch-up holding current (lhold_lu) from developing, thus preventing latch-up from occurring. Current limiter () can include p-channel transistors and/or resistors, and thus consume a relatively small area of the memory device.