The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2007
Filed:
Feb. 16, 2000
Yasushi Kubota, Sakurai, JP;
Hajime Washio, Tenri, JP;
Ichiro Shiraki, Tenri, JP;
Kazuhiro Maeda, Tenri, JP;
Yasuyoshi Kaise, Tenri, JP;
Yasushi Kubota, Sakurai, JP;
Hajime Washio, Tenri, JP;
Ichiro Shiraki, Tenri, JP;
Kazuhiro Maeda, Tenri, JP;
Yasuyoshi Kaise, Tenri, JP;
Sharp Kabushiki Kaisha, Osaka, JP;
Abstract
A CMOS logical circuit comprises two electric current paths each of which has circuits consisting of n-type and p-type transistors. In a circuit consisting of n-type or p-type transistors, one electric current path is provided with a circuit having the same construction as that of a circuit having an n-type transistor of a CMOS logical circuit outputting a logical operation result similar to that of this logical circuit, and the other electric current path is provided with a circuit having the same construction as that of a circuit having a p-type transistor of the CMOS logical circuit outputting a logical operation result similar to that of this logical circuit. In another circuit consisting of the other channel type, a gate electrode of the transistor provided on the one electric current path and that of the transistor provided on the other electric current path are connected to drain electrodes of the counterparts. According to the construction, the amplitude of an input signal can be made smaller than a supply voltage of the logical circuit.