Programmable clock drivers that support crc error checking of configuration data during program restore operations

Abstract

A packaged integrated circuit device includes a nonvolatile memory device and a programmable clock driver circuit therein. The memory device may be provided as an EEPROM device that is disposed on a first integrated circuit substrate and the programmable clock driver circuit may be disposed on a second integrated circuit substrate. The programmable clock driver circuit includes a control circuit and a clock generator therein. The control circuit is configured to detect an error(s) in configuration data that is used by the programmable clock driver circuit. This configuration data is read from the nonvolatile memory and stored in volatile program registers during program restore operations. The control circuit is further configured to automatically idle the clock generator in response to detecting the error in the configuration data. This automatic idling of the clock generator may include operations to set the clock generator at a default setting (e.g., minimum frequency), which applies to all output banks of the driver circuit.