The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2007

Filed:

Aug. 25, 2004
Applicants:

Dipankar Bhattacharya, Macungie, PA (US);

John C. Kriz, Palmerton, PA (US);

Duane J. Loeper, Spring City, PA (US);

Antonio M. Marques, Summit, NJ (US);

Inventors:

Dipankar Bhattacharya, Macungie, PA (US);

John C. Kriz, Palmerton, PA (US);

Duane J. Loeper, Spring City, PA (US);

Antonio M. Marques, Summit, NJ (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A PUR circuit for generating a reset signal includes a first node for receiving a reference voltage and a second node for receiving a supply voltage that is referenced with respect to the reference voltage. The circuit further includes a voltage level detector coupled between the first node and a third node, the voltage level detector being configured to generate a first control signal at the third node. The voltage level detector includes a first transistor having a first threshold voltage associated therewith. A resistance element is coupled between the second node and the third node, the resistance element having a first resistance value associated therewith. The circuit also includes an inverter having an input coupled to the third node and having an output for generating a second control signal in response to the first control signal. The inverter includes a second transistor having a second threshold voltage associated therewith which is lower than the first threshold voltage. The voltage level detector is configured such that the first control signal is substantially equal to the supply voltage when the supply voltage is less than a first voltage, and the first control signal is equal to a second voltage when the supply voltage is substantially equal to or greater than the first voltage. The second voltage is less than a lower switching point of the inverter, the first voltage being based at least in part on the first threshold voltage, the reset signal being a function of the second control signal.


Find Patent Forward Citations

Loading…