The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 27, 2007
Filed:
Jan. 22, 2003
Khai Nguyen, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
IN Whan Kim, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Richard G Cliff, Milpitas, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie I Wang, Cupertino, CA (US);
Wayne Yeung, San Francisco, CA (US);
Khai Nguyen, San Jose, CA (US);
Xiaobao Wang, Santa Clara, CA (US);
In Whan Kim, San Jose, CA (US);
Chiakang Sung, Milpitas, CA (US);
Richard G Cliff, Milpitas, CA (US);
Joseph Huang, San Jose, CA (US);
Bonnie I Wang, Cupertino, CA (US);
Wayne Yeung, San Francisco, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A programmable logic device is equipped for low voltage differential signaling ('LVDS') by providing an LVDS input buffer and/or an LVDS output buffer on the device. I/O pins on the device that are used together in pairs for LVDS can alternatively be used individually for other types of signaling. The LVDS buffers are constructed to give good performance and to meet LVDS specifications despite variations due to temperature, manufacturing process inconsistency, and power supply changes.