The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2007

Filed:

Mar. 29, 2004
Applicant:

Kenji Ichikawa, Tokyo, JP;

Inventor:

Kenji Ichikawa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/62 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor apparatus where output and protection transistors are different in transistor structure, and where, even when breakdown in the output transistor occurs earlier than in the protection transistor, an ESD surge current does not concentrate in the output transistor inferior in ESD resistance. Formed in its output circuit, where the drain and source of a first-conductivity-type, e.g. NMOS, output transistorare connected respectively to an output electrode and to ground, is an NMOS protection transistorof which the drain and source are connected respectively to the drain and source of the NMOS output transistorand of which the gate is directly connected to a second-conductivity-type layer, a P-well, under the gate electrode of the NMOS output transistor. By this means, an electrostatic surge does not concentrate in the NMOS output transistor


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