The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 27, 2007

Filed:

Sep. 29, 2003
Applicants:

Samuel M. Babb, Ft Collins, CO (US);

Lowell E Kolb, Loveland, CO (US);

Brian Davis, Fort Collins, CO (US);

Jonathan P Mankin, Fort Collins, CA (US);

Kristina L Mann, Fort Collins, CO (US);

Paul H Mazurkiewicz, Fort Collins, CO (US);

Marvin Wahlen, Loveland, CO (US);

Inventors:

Samuel M. Babb, Ft Collins, CO (US);

Lowell E Kolb, Loveland, CO (US);

Brian Davis, Fort Collins, CO (US);

Jonathan P Mankin, Fort Collins, CA (US);

Kristina L Mann, Fort Collins, CO (US);

Paul H Mazurkiewicz, Fort Collins, CO (US);

Marvin Wahlen, Loveland, CO (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 9/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electrically continuous, grounded conformal EMI protective shield and methods for applying same directly to the surfaces of a printed circuit board. The EMI shield adheres and conforms to the surface of the components and printed wiring board. The shield takes the shape of the covered surfaces while adding little to the dimensions of the surfaces. The EMI shield includes low viscosity, high adherence conductive and dielectric coatings each of which can be applied in one or more layers using conventional spray techniques. The conductive coating prevents substantially all electromagnetic emissions generated by the shielded components from emanating beyond the conformal coating. The dielectric coating is initially applied to selected locations of the printed circuit board so as to be interposed between the conductive coating and the printed circuit board, preventing the conductive coating from electrically contacting selected components and printed wiring board regions.


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