The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7194724 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 20, 2007

Filed:

Nov. 16, 2004
Applicants:

Dai Hattori, Otsu, JP;

Osamu Ogawa, Neyagawa, JP;

Keiichi Kurokawa, Takarazuka, JP;

Inventors:

Dai Hattori, Otsu, JP;

Osamu Ogawa, Neyagawa, JP;

Keiichi Kurokawa, Takarazuka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

First of all, the number of referencing of a variable described in a behavior level circuit is calculated. Next, a bit width of the variable is extracted, and a plurality of memories capable of data transferring of the extracted bit width are selected. Next, a sum of a frequency of memory access for each of the selected plurality of memories when the variable is allocated thereto is calculated based on the number of referencing and the bit width of the variable. After that, as a target for allocating the variable, a memory that minimizes the calculated sum of the frequency of the memory access is selected.


Find Patent Forward Citations

Hattori, Dai. (2007). High level synthesis method and high level synthesis apparatus (U.S. Patent No. 7194724). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7194724

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