The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Mar. 14, 2003
Kumar Deepak, San Jose, CA (US);
L. James Hwang, Menlo Park, CA (US);
Singh Vinay Jitendra, Fremont, CA (US);
Haibing MA, Superior, CO (US);
Roger B. Milne, Boulder, CO (US);
Nabeel Shirazi, San Jose, CA (US);
Jeffrey D. Stroomer, Lafayette, CO (US);
Jimmy Zhenming Wang, Saratoga, CA (US);
Kumar Deepak, San Jose, CA (US);
L. James Hwang, Menlo Park, CA (US);
Singh Vinay Jitendra, Fremont, CA (US);
Haibing Ma, Superior, CO (US);
Roger B. Milne, Boulder, CO (US);
Nabeel Shirazi, San Jose, CA (US);
Jeffrey D. Stroomer, Lafayette, CO (US);
Jimmy Zhenming Wang, Saratoga, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method, apparatus, and computer readable medium for simulating an integrated circuit within a modeling system using one or more circuit description language representations of circuitry is described. By example, a circuit description language representation of the one or more circuit description language representations of circuitry is translated into a program language circuit description. A first simulation process is executed and input data is obtained therefrom. A second simulation process is executed with the input data as parametric input to produce output data, the second simulation process being derived from the program language circuit description. The output data produce by the second simulation process is provided to the first simulation process.