The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Oct. 22, 2002
Sanjay Dubey, Sunnyvale, CA (US);
Yoganand Chillarige, Sunnyvale, CA (US);
Shivakumar Sompur, Sunnyvale, CA (US);
Ban P. Wong, Milpitas, CA (US);
Cynthia Tran, San Jose, CA (US);
Sanjay Dubey, Sunnyvale, CA (US);
Yoganand Chillarige, Sunnyvale, CA (US);
Shivakumar Sompur, Sunnyvale, CA (US);
Ban P. Wong, Milpitas, CA (US);
Cynthia Tran, San Jose, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
An arithmetic logic unit (ALU) implemented with complementary pass gate logic using propagate, generate, and kill is provided. Broadly speaking, the ALU is a 64-bit ALU using a multi-stage global carry chain to generate intermediate fourth-bit carries that are folded with local four-bit sums to efficiently generate a final sum output. The ALU implements ones complement subtraction by incorporating a subtraction select signal to invert each bit of a second operand. The ALU circuitry implements a push-pull methodology to improve performance.