The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 20, 2007
Filed:
Sep. 16, 2005
Paul John Morrow, Limerick, IE;
Maria Del Mar Chamarro Marti, Valencia, ES;
Colin G. Lyden, Cork, IE;
Mike Dominic Keane, Limerick, IE;
Robert W. Adams, Acton, MA (US);
Richard Thomas O'brien, Limerick, IE;
Paschal Thomas Minogue, Limerick, IE;
Hans Johan Olaf Mansson, Limerick, IE;
Paul John Morrow, Limerick, IE;
Maria del Mar Chamarro Marti, Valencia, ES;
Colin G. Lyden, Cork, IE;
Mike Dominic Keane, Limerick, IE;
Robert W. Adams, Acton, MA (US);
Richard Thomas O'Brien, Limerick, IE;
Paschal Thomas Minogue, Limerick, IE;
Hans Johan Olaf Mansson, Limerick, IE;
Analog Devices, Inc., Norwood, MA (US);
Abstract
A multi-bit continuous-time sigma-delta analog-to-digital converter (ADC) has a differential input stage which receives an analog input signal current. A multi-bit feedback current digital-to-analog converter (IDAC) generates a multi-level feedback current depending on a digital feedback signal from a flash ADC. An integrator has a differential input that integrates the difference of the generated current by the multi-bit IDAC and the input signal current on a continuous-time basis. The input stage further comprises a first biasing current source and a second biasing current source which bias the input stage in a mid-scale condition. A first summing node connects to the first differential input line, a first differential input of the integrator and the first output branch. A second summing node connects to the second differential input line, a second differential input of the integrator and the second output branch. A set of chopping switches alternately connect the biasing current sources to the summing nodes in a first configuration and a second, reversed, configuration. The converter receives a modulator clock signal at a frequency Fand the chopping switches can operate at For a binary subdivision thereof. The integrator amplifier can also be chopper-stabilized.