The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Apr. 23, 2004
Sunil Kumar Sharma, Uttar Pradash, IN;
Ajay Tomar, Uttar Pradesh, IN;
Dhabalendu Samanta, Delhi, IN;
Sunil Kumar Sharma, Uttar Pradash, IN;
Ajay Tomar, Uttar Pradesh, IN;
Dhabalendu Samanta, Delhi, IN;
STMicroelectonics PVT Ltd., Uttar Pradesh, IN;
Abstract
The method for mapping a logic circuit to a plurality of interconnectable, programmable look up tables (LUT) elements includes forming logic element groups including individual logic elements and/or previously formed logic element groups that are capable of being accommodated within the fanin and/or fanout capacity of a target LUT. The method further includes mapping the formed logic element group to the target LUT, and repeating the process for forming logic element groups and mapping to target LUTs for the entire network in a manner such that at each stage only the unmapped logic element/elements and mapped logic element groups of the previous stage are considered for mapping.