The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2007

Filed:

May. 26, 2004
Applicants:

Bernard Tourancheau, Miribel, FR;

Xavier-francois Vigouroux, Brie et Angonnes, FR;

Cedric Koch-hofer, Saint Martin d'Heres, FR;

Inventors:

Bernard Tourancheau, Miribel, FR;

Xavier-Francois Vigouroux, Brie et Angonnes, FR;

Cedric Koch-Hofer, Saint Martin d'Heres, FR;

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system and method for determining a carrier layout using cornered chip-to-chip input/output is presented. Each of a plurality of individual integrated circuit carriers communicatively interfaceable through cornered input/output ports is oriented at a uniform rotation relative to an edge of a carrier layout. Each carrier defines a set of rectilinear edges. Each carrier is placed juxtaposed at an open corner to at least one other carrier within a rectilinear lattice topologically arranged in the carrier layout to substantially minimize Hamming distances between each of the carriers.


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