The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Jun. 04, 2004
Yufeng Luo, San Jose, CA (US);
Prasanna Venkat Srinivas, Cupertino, CA (US);
Shankar Krishnamoorthy, Saratoga, CA (US);
Yufeng Luo, San Jose, CA (US);
Prasanna Venkat Srinivas, Cupertino, CA (US);
Shankar Krishnamoorthy, Saratoga, CA (US);
Sierra Design Automation, Inc., Santa Clara, CA (US);
Abstract
A method and apparatus is described which allows efficient optimization of integrated circuit designs. By performing a global analysis of the circuit and identifying bottleneck nodes, optimization focuses on the nodes most likely to generate the highest return on investment and those that have the highest room for improvement. The identification of bottleneck nodes is seamlessly integrated into the timing analysis of the circuit design. Nodes are given a bottleneck number, which represents how important they are in meeting the objective function. By optimizing in order of highest bottleneck number, the optimization process converges quickly and will not get side-tracked by paths that cannot be improved.