The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2007
Filed:
Sep. 28, 2005
Wei Lin, Santa Clara, CA (US);
Sushama Ghanekar, San Jose, CA (US);
Jimmy Zhenming Wang, Saratoga, CA (US);
Kumar Deepak, San Jose, CA (US);
Wei Lin, Santa Clara, CA (US);
Sushama Ghanekar, San Jose, CA (US);
Jimmy Zhenming Wang, Saratoga, CA (US);
Kumar Deepak, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Method and apparatus for processing a circuit description including a hierarchy of components for logic simulation is described. Each component is described using one of a first hardware description language (HDL) and a second HDL. A root component and each component in the hierarchy below the root component described using an HDL identical to that of the root component is elaborated up to a cross-language boundary. The root component is described using one of the first HDL or the second HDL and each component at the cross-language boundary is described using the other of the first HDL or the second HDL. Each component at the cross-language boundary is stored in one of a first vector associated with the first HDL or a second vector associated with the second HDL based on language. A connection is established between each component at the cross-language boundary and a respective parent component.